Conventionally, integrated circuit wafers range from 100 to 300 millimeters in diameter and are cut (or diced) into individual die using sawing or “scribe and crack” methods. This process is also sometimes called singulation. These methods typically require a minimum 25 micro-meter kerf or spacing between the die. They are also subject to chipping which often adds 10 to 100 micro-meters to this dimension. In addition the technology used for mounting the wafer to the separation tool will not allow the fabrication of ultra small die as they tend to release prematurely. These dicing technologies are generally limited to straight line cuts. Furthermore with large wafers and small die, more cuts are required making the dicing time prohibitive or at least more costly. In addition, if the die dimension is close to that of the kerf, a large fraction of the wafer is wasted.
What is needed is a rapid, cost effective method that allows very small die or irregularly shaped die to be singulated from a large wafer using a method that is compatible with existing semiconductor foundry practice.